Plato Assignment Example | Topics and Well Written Essays - 250 words

Plato - Assignment Example Plato’s thoughts and theories have been used to teach many subjects, from religion to mathematics. Plato’s dialogues, in which he addressed almost all controversial philosophical topics of his time, have become the bread and butter of modern philosophers. The dialogues contain critical and thought-provoking analyses of intricate subjects, some of which were considered â€Å"untouchable† at the time. However, the application of the dialogues is not restricted to philosophy (Pojman and Vaughn 34). Any normal person can use the thoughts they contain to develop or enhance critical thinking skills and to gain a clear perspective of life. For instance, the Apology, the Symposium, the Cratylus, and the Phaedrus can be used to improve students’ critical thinking capacities and encourage them to consider philosophy as a crucial aspect of life. Plato’s teachings embody the triumphs of the human race in trying to harness the power of the mind (Pojman and Vaughn 26). They also represent the endless possibilities and capacities of human intellect, and encourage us to question and debate everything around

Influence of Social Networking Sites on Relationships Essay

Influence of Social Networking Sites on Relationships - Essay Example The essay "Influence of Social Networking Sites on Relationships" discusses the influence of social networking sites on relationships. A social networking site is a form of media of the digital age that helps people in the development of communities and networks. Some of the most popular examples include Facebook, Twitter, and Orkut. The system of kinship includes people who have close relationships with each other or those who are living as a unit or family. We create our own definition of family. We can decide to add and not add people depending on whether we trust them or consider them family. In this way, we actually go beyond defining kinship as just blood relationships and add such relationships to the definition that leaves a great impact on our lives. Some people believe that close relationships fall into the definition of kinship whereas some people believe that only a blood relationship is real kinship. Today, anthropology is heading towards forming new forms of kinship. Fo r example, we can find many people on Facebook who have their close friends or childhood friends as their sisters and brothers. On the other hand, many people present on Facebook have blood relationships between each other. Social networking sites, such as Facebook, also helps people in the formation of imagined communities and networks. People can form such communities where there are no boundaries, no nation states, but a place where they can find people with whom they feel good. Facebook has made people less individualistic.

Childhood Essay Example for Free

Childhood Essay Be able to develop positive relationships with children and young people Explain why positive relationships with children and young people are important and how these are built and maintained. Positive relationships with children and young people are important for the child so that they can learn and develop to their full ability. If a child feels comfortable with you they would be more inclined to leave their parents in the morning easier. This makes the parent feel happier – leaving their child with someone their child enjoys being – and makes them feel less guilty about going to work. This also then means they can start to play and interact with other children. Through playing and exploring and socialising the child or young person will then start to participate in more and more activities. A good relationship with the child means you make them feel safe and secure and if the child has positive emotions it is more likely they will stay healthier and not get run down or ill. A positive relationship is also important because it is then less likely that the child will act out and behave negatively. They are less likely to act out and behave negatively if the child has a positive bond with you because you will know them well enough to cater for their wants, wishes and individual needs, therefore they will not feel frustrated or alone and will not need to act out to relieve stress or anger or to gain attention. A positive relationship is important as it helps a child develop confidence at a quicker rate and develop their language and communication skills quicker too. If a child feels comfortable with you they will start to talk to you more, providing you with the opportunity to assess where the child is at developmentally with their speech, language, knowledge and other aspects, and also find out about their personal interests. You can then set activities to help the child to further develop based on what they can already do and ensure the activity will fun for them by incorporating their interests into the activity. This means they can start to develop quicker and with the help of someone they have a positive relationship with. Having a positive relationship with a child will mean you know them well, their personality, their emotions, the little things. Therefor you can easily pick up on a difference in body language to know if there is something wrong, and also you begin to know what facial expression means what and so can address any issues quicker. Also with a positive relationship the child will feel like they can come to you and this is important so that they do not keep anything inside and instead share and resolve the issue so they feel calm again and happiness is essential in childhood. A positive relationship is built through trust. It’s the little things you do that helps you build up a positive relationship with the child. For example: Giving them praise for doing something good Giving them a cuddle when they need it Helping and supporting them through the daily routine Keeping them safe and feeling secure having a positive relationship with their parents. All of these are ways to build and maintain a relationship with the child or young person and their career. Children and young people like consistency and stability, they like what they know and as long as you can be or are there for them consistently, and are positive towards them they will begin to form a bond with you. Evaluate own effectiveness in building relationships with children or young people When settling a new child into my room there are a few things I do to make them feel comfortable and hopefully build a positive relationship with them. Firstly, when a child or young person enters the room I always make sure I greet them, making eye contact, saying hello and smiling. I make sure I get down to their level and offer to give them a hug. I try to make the environment they walk into a positive one so they do not feel threatened or intimidated but more welcomed and wanted. I think this is effective as it is becomes a routine they can get used to seeing me when they walk through the door and will then instinctively start to say hello back and accept your offer of a hug. I also ensure I am always happy and have a chat with their parent or guardian. I think if the parent and you have a positive relationship the child will pick up on this and start react that way too. I think it’s an effective method to use as they do not see you as ‘the person that takes them away from their parent or guardian’ but instead sees you as a friend of theirs and their parent/guardian. I also find another very effective way to build a positive relationship with a child or young person is to constantly encourage them. Giving them a variety of toys and saying ‘oh what’s this? Would you like to play in the sand? ’ ect. This promotes to them you are fun and want to play with them. Children usually like someone to play with however this is not always effective if the child’s individual preference is to be left alone. In which case it is better to build the relationship by giving them their space, but making sure you are there for them when they need you for example, they are upset and you give them cuddles and/or words of reassurance. We recently had a little girl start and every day she will sit at the breakfast table. For a couple of weeks now I have been smiling at her and asking if she wants to come play. In the past she hasn’t, but by not being too pushy and letting her settle in at her own pace, she has started to smile back and will sometimes gain the confidence to come and join me in playing in the sand for example. Therefore, patience, understanding but persevering too is an effective way to build a relationship with the child, letting them have their own time to get used to you, trust you and like you. A method I use to build a relationship with a child is to just always be in the room paying and having fun. If a new child see’s you having fun playing and the children you are with doing so too they will normally begin to do so to. I think this is effective because the ‘fun factor’ is something I have found no child can resist. Also the fact that you are always there they can get used to you quicker the more you are available to them. If you ask the children or young people questions I find they begin to come out of themselves more, however there is the potential of a language barrier and so the effectiveness of asking question is non-existent. In this case it is effective to learn some of the child’s key words in their language and communication is an effective way of building a bond with a child. If you are seen to be trying the child will recognise this and begin to try to. I have in the past learnt key words in another language and began to say it in their language and then English, this has been effective as they have wanted to learn and hey used to come ad sit with me a lot just practicing these few English words. However, I only found this effective once the child had settled into the setting and was used to being there.

Is music still true?

Is music still true? Is Music Still True? Authenticity is a major issue in popular music, and it also seems to verify the differences between ‘rock and ‘pop. To musicians, rock is the genre that has authenticity and is most trusted, while the pop genre tends to be more of a commercialized type of music, which most musicians today believe that the ‘pop music is about the glamour and the money. In the end it comes down to the listeners point of view. In this argument, authenticity is understood as ‘true to its origins. Some say that with the new technology today, its hard to make anything sound authentic. In some cases, for example Jack White from such bands as The White Stripes, The Raconteurs, and The dead Weather, have stayed away from technology when it comes to the recording end. White also attempts to capture authenticity by using old instruments, to capture the essence of the old time sound. Like White, other artists as well find that the new technology today takes the ‘soul out of the music, as well as go far enough to use authentic old style instruments. Although some believe that you can use technology today to give it even more of a rich authentic sound. Most people believe that ‘soul is the key component to authenticity, while some believe that it is about reenacting the innovators of the past. Some believe that songs or artists can still have authentic meaning. One artists that has dealt with issues of authenticity was 60s folk star Bob Dylan. Dylans first electric album rainy day woman had a enormous impact on his fans. The fans were enraged at his desertion from the authentic folk roots that he was so well known for. He received some credit with the fact that his lyrics and song topics were still awarded as authentic. Dylans song were known to make a strong stand toward politics, and had simple lyrics but had complex understanding. Then there are artists like John Mayer, who keep to the authenticity on every level, but seems to add his own modern twist. Mayer is a well known blues guitarist who keeps to his ‘bluesy guitar riffs, but with a sound of a distorted guitar. Mayer at times has also been subjected to the ‘pop commercial genre, with his higher pitched voice and for his criticized lyrics. Artists like these prove that authenticity in music, does not mean that it has to be exactly like the origins it came from. Certain authors have pondered that this distinction may be misleading, but even so, have divided authenticity into several categories (Moore, 2002): first person authenticity, where original music is performed in a manner that makes the audience believe the music is authentic: that is, authentically created, and performed; and third person authenticity, where a performer of music succeeds in conveying the impression of having accurately conveyed the expression of an – absent – other (Moore, 2002). Authenticity is assumed, by many authors, to be inscribed to a musician or performer, yet this assumption is wholly wrong, in that authenticity is actually ascribed to musicians and performers. Authenticity, as a value, is something that must be constructed by each and every listener personally, according to their own response to the music in question. It is only after the listener sees the performance of the music by the musician, that they can begin to understand the musicians relationship to the piece, and their interpretation of the piece, and only then can the musician be said to have any authenticity. The following is based on this view of authenticity as an ascribed value. Eric Clapton and his music are used as an example by many authors on the subject of authenticity in music, and these discussions invariably fall into Moores (2002) second category of authenticity: third-person authenticity. Eric Clapton, a highly able and respected musician, gained a huge worldwide following in the 1960s for his interpretations and performances, solo and with his band, Cream. I say ‘interpretation as many of the songs that Clapton, and Cream performed, such as Crossroads, were not original songs, and were re-worked by Clapton. Crossroads was a song originally written and performed by the country blues star Robert Johnson (Moore, 2002). Johnson led a tragic life, dying early in mysterious circumstances, and living his life as a poor man, with only his guitar for comfort, on which he composed blues music, through which he explored his own life through distorting the sound of the instrument to provide an analogue for his own tortured soul (Moore, 2002). It is argued that, to a certain extent, when Clapton performed Crossroads, he did not authenticate Johnsons music by reinforcement, rather his interpretation of Johnsons song authenticated Claptons own musical presence (Moore, 2002). It was the appropriation of the ‘black blues tradition, of which Johnson was a part, which gave Clapton the material through which he constructed himself as an authentic performer (Moore, 2002). Claptons appropriation of the ‘black blues tradition was then cemented by his full discovery of this tradition, from BB King to Freddie and Albert King, from country blues through to Robert Johnson (Moore, 2002). This tracing of the origins of a practice back to the originator of the practice thus reinforces the tradition to the tracer: this phenomenon, and is well known in discussions of authenticity in popular music (Moore, 2002); this process is also necessarily circular, as Clapton was authenticated via his appropriation of Johnson, who was then authenticated by his appropriation by an artist he himself had a great deal of respect for (Moore, 2002), since only music that is worth acquiring will be appropriated. As Moore (2002) argues, Clapton conveyed the message ‘this is what it is like to be me to his audience, using the message ‘this is what it was like to be Johnson. Thus, authenticity of execution (Moore, 2002) arises when a performer succeeds in conveying the impression of accurately conveying the expression of an absent other (Moore, 2002), and Clapton is a particularly apt example of this third-person authenticity. Thus, during his performances of particular songs (for example, Crossroads) Clapton speaks the truth of his own situation, as during his performances, he can only convey his own particular expression of a particular song openly, honestly and therefore, truthfully. As to whether Clapton manages to convey the truth of the situation of absent others, this is a difficult one to answer. In order for an audience to believe that Clapton is conveying the truth of an absent other, the audience needs to know that Clapton has respect for that absent other, enough respect to have made a thorough study of the tradition to which that musician belonged, a study which allows Claptons interpretation of that particular piece of music to be authentic in the sense of being true to its origins. As to whether Clapton speaks the truth of his own culture and thereby represents present others when performing the music of absent others, this is an even more difficult point of discussion. This point needs to rely on a meaning for the word ‘culture in order to fully answer this question, and this is difficult. Can Clapton, a white man, from a white culture, ever delve deeply enough in to a tradition to be able to authentically convey music from an entirely different (‘black) culture? Cultural purists would argue not, but in todays multicultural society, the answer to this question is increasingly (and increasingly believably) likely to be yes, at least for white audiences, and for ‘blacks who agree with the idea, and principles, of cross-cultural artistic expression. However, it has to be recognized that there are certain tensions and resistance encountered in the process of cross-cultural appropriation of music, particularly in this case, as it concerns the black community, who see their musical heritage as something pure, a badge of identity entirely their own. This is entirely understandable, particularly in reference to appropriation of the blues tradition by whites, as blues is a black music, which arose out of unspeakable suppression and hardship at the hands of the white man. Tensions that arise from within the black community at the (mis)use of the blues tradition by whites should therefore be listened to, and could also be used as a lesson to learn from. A recent book by Todd Gitlin (2001) argues that we, as a society, are becoming so overwhelmed with information from the media, in so many varieties of the media, that we are becoming immune to its lure, and are even beginning to shy away from this media onslaught. It seems that one way people can avoid this media onslaught is to search out authentic performances from authentic musicians, as this would guarantee quality and purity of enjoyment. Authenticity of an artists like Clapton, really come down to the listeners and their opinion on whether or not the artists is authentic. Music has always been about the listeners, so they are the only ones who can really decide what is authentic. Most fans will say the authentic ones are the ones who ‘keep it real, which is just another way of saying keeping it true to the original genre. Which makes Authenticity in music a very long ongoing topic. There will always be those who say ‘he is to commercial for me and those who will think that that artists perfected and recreated a new side of the authentic origin. Artists, like Clapton, who appropriate music from other cultures, and who we can argue do this in a compassionate manner, are perhaps the guiding lights for many of todays media-overwhelmed generation; they serve, for many, as a good introduction to the traditions from which such music is drawn, from which point the interested can do their own research and discover the authentic music from which such adaptations are developed. Cross-cultural musical evolution can only be a process for good in terms of the development of music, as long as authenticity and the ‘donor culture are respected.

Synopsys For Physical Design Of Asic Computer Science Essay

Synopsys For Physical Design Of Asic Computer Science Essay IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16] 4.2 User Interfaces IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts. The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges. To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides. IC Compiler design flow involves execution of following steps: 1. Set up and prepare the libraries and the design data. 2. Perform design planning and power planning. -Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads. -Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current. 3. Perform placement and optimization. IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations. To perform placement and optimization, use the place_opt core command (or from GUI choose Placement menu and then Core Placement and Optimization sub-menu). 4. Perform clock tree synthesis and optimization. To perform the clock tree synthesis and optimization phase, use the command clock_opt (or choose Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays. 5. Perform routing and postroute optimization. To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI). As part of routing and postroute optimization, IC Compiler performs global routing, track assignment, detail routing, search and repair, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the routing and postroute optimization functions for special needs. 6. Perform chip finishing and design for manufacturing tasks. IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing. 7. Save the design. Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16] 4.3 How to Invoke the IC Compiler 1. Log in to the UNIX environment with the user id and password . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix prompt turns into the IC Compiler shell command prompt. 3. Start the GUI. icc_shell> start_gui This window can display schematics and logical browsers, among other things, once a design is loaded. 4.4 Preparing the Design IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format. These steps are explained in the following sections: à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã‚ ¢ Reading the Design à ¢Ã¢â€š ¬Ã‚ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã‚ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Logic Libraries: IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs. IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries: à ¢Ã¢â€š ¬Ã‚ ¢ search_path Lists the paths where IC Compiler can locate the logic libraries. à ¢Ã¢â€š ¬Ã‚ ¢ target_library Lists the logic libraries that IC Compiler can use to perform physical optimization. à ¢Ã¢â€š ¬Ã‚ ¢ link_library Lists the logic libraries that IC Compiler can search to resolve references. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Physical Libraries: IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific. The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks. If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design. This section describes how to perform the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Create a Milkyway design library To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Open a Milkyway design library To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Report on a Milkyway design library To report on the reference libraries attached to the design library, use the -mw_reference_library option. icc_shell>report_mw_lib-mw_reference_library design_library_name To report on the units used in the design library, use the report_units command. icc_shell> report_units à ¢Ã¢â€š ¬Ã‚ ¢ Change the physical library information To change the technology file, use the set_mw_technology_file command (or choose File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library. à ¢Ã¢â€š ¬Ã‚ ¢ Save the physical library information To save the technology or reference control information in a file for later use, use the write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice. à ¢Ã¢â€š ¬Ã‚ ¢ Verifying Library Consistency: Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16] icc_shell> check_library 4.4.2 Setting Up the Power and Ground Nets IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets: à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic0_net By default, IC Compiler VSS as the ground net name. If you are using a different name, you must specify the name by setting the mw_logic0_net variable. à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic1_net By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable. 4.4.3 Reading the Design IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in Milkyway Format à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in ASCII Format 4.4.4 Annotating the Physical Data IC Compiler provides several methods of annotating physical data on the design: à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a DEF file To read a DEF file, use the read_def command (or choose File > Import > Read DEF in the GUI). icc_shell> read_def -allow_physical design_name.def à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a floorplan file A floorplan file is a file that you previously created by using the write_floorplan command (or by choosing Floorplan > Write Floorplan in the GUI). icc_shell> read_floorplan floorplan_file_name à ¢Ã¢â€š ¬Ã‚ ¢ Copying the physical data from another design To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16] icc_shell> copy_floorplan -from design1 4.4.5 Preparing for Timing Analysis and RC Calculation IC Compiler provides RC calculation technology and timing analysis capabilities for both preroute and postroute data. Before you perform RC calculation and timing analysis, you must complete the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Set up the TLUPlus files You specify these files by using the set_tlu_plus_files command (or by choosing File > Set TLU+ in the GUI). icc_shell> set_tlu_plus_files -tech2itf_map ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/best_settings.tlup à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Back-annotate delay or parasitic data To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI). To remove annotated data from design, use the remove_annotations command. à ¢Ã¢â€š ¬Ã‚ ¢ Set the timing constraints At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing. To read a timing constraints file, use the read_sdc command (or choose File > Import > Read SDC in the GUI). icc_shell> read_sdc -version 1.7 design_name.sdc à ¢Ã¢â€š ¬Ã‚ ¢ Specify the analysis mode Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. The set_operating_conditions command specifies the operating conditions for analysis. à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Set the derating factors If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. à ¢Ã¢â€š ¬Ã‚ ¢ Select the delay calculation algorithm By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16] 4.4.6 Saving the Design To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16] CHAPTER 5: Design Planning 5.1 Introduction Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment. Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16] Figure 5.1 IC Compiler Design Planning [21] 5.2 Tasks to be performed during Design Planning à ¢Ã¢â€š ¬Ã‚ ¢ Initializing the Floorplan à ¢Ã¢â€š ¬Ã‚ ¢ Automating Die Size Exploration à ¢Ã¢â€š ¬Ã‚ ¢ Handling Black Boxes à ¢Ã¢â€š ¬Ã‚ ¢ Performing an Initial Virtual Flat Placement à ¢Ã¢â€š ¬Ã‚ ¢ Creating and Shaping Plan Groups à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing Prototype Global Routing à ¢Ã¢â€š ¬Ã‚ ¢ Performing Hierarchical Clock Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing In-Place Optimization à ¢Ã¢â€š ¬Ã‚ ¢ Performing Routing-Based Pin Assignment à ¢Ã¢â€š ¬Ã‚ ¢ Performing RC Extraction à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Analysis à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Budgeting à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Physical Hierarchy à ¢Ã¢â€š ¬Ã‚ ¢ Refining the Pin Assignment 5.3 Initializing the Floorplan The steps in initializing the floorplan are described below. à ¢Ã¢â€š ¬Ã‚ ¢ Reading the I/O Constraints: To load the top-level I/O pad and pin constraints, use the read_io_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Defining the Core and Placing the I/O Pads: To define the core and place the I/O pads and pins, use the initialize_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Rectilinear-Shaped Blocks: Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X. à ¢Ã¢â€š ¬Ã‚ ¢ Writing I/O Constraint Information: To write top-level I/O pad or pin constraints, use the write_io_constraints command. Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Cell Rows: To add cell rows, use the add_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Removing Cell Rows: To remove cell rows, use the cut_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Floorplan Information: To save the floorplan information, use the write_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢Writing Floorplan Physical Constraints for Design Compiler Topographical Technology: IC Compiler can now write out the floorplan physical constraints for Design Compiler Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is: write_physical_constraints -output output_file_name -port_side [16] Figure 5.2 Floor Plan After Initialization [21] 5.4 Automating Die Size Exploration This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view. 5.5 Handling Black Boxes Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan. To handle the black boxes run the following set of commands. set_fp_base_gate estimate_fp_black_boxes flatten_fp_black_boxes create_fp_placement place_fp_pins create_qtm_model qtm_bb set_qtm_technology -lib library_name create_qtm_port -type clock $port report_qtm_model write_qtm_model -format qtm_bb report_timing qtm_bb 5.6 Performing an Initial Virtual Flat Placement The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing. The way to perform an initial virtual flat placement is described below. à ¢Ã¢â€š ¬Ã‚ ¢ Evaluating Initial Hard Macro Placement: No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience. à ¢Ã¢â€š ¬Ã‚ ¢ Specifying Hard Macro Placement Constraints: Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement. Creating a User-Defined Array of Hard Macros Setting Floorplan Placement Constraints On Macro Cells Placing a Macro Cell Relative to an Anchor Object Using a Virtual Flat Placement Strategy Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch Creating Macro Blockages for Hard Macros Padding the Hard Macros à ¢Ã¢â€š ¬Ã‚ ¢ Padding the Hard Macros: To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macros edges. [16] To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. à ¢Ã¢â€š ¬Ã‚ ¢ Placing Hard Macros and Standard Cells: To place the hard macros and standard cells simultaneously, use the create_fp_placement command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Floorplan Editing: IC Compiler performs the following floorplan editing operations. Creating objects Deleting objects Undoing and redoing edit changes Moving objects Changing the way objects snap to a grid Aligning movable objects 5.7 Creating and Shaping Plan Groups This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros. The following steps are covered for Creating and Shaping Plan Groups. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Plan Groups: To create a plan group, create_plan_groups command. To remove (delete) plan groups from the current design, use the remove_plan_groups command. à ¢Ã¢â€š ¬Ã‚ ¢ Automatically Placing and Shaping Objects In a Design Core: Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped. To automatically place and shape objects in the design core, shape_fp_blocks command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Padding to Plan Groups: To prevent congestion or DRC violations, one can add padding around plan group boundaries. Plan group padding sets placement blockages on the internal and external edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding. To add padding to plan groups, create_fp_plan_group_padding command. To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Block Shielding to Plan Groups or Soft Macros: When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro. To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command. To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16] 5.8 Performing Power Planning After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Logical Power and Ground Connections: To define power and ground connections, use the connect_pg_nets command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Rings: It is necessary to add power and ground rings after doing floorplanning. To add power and ground rings, use the create_rectangular_rings command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Straps: To add power and ground straps, use the create_power_straps command. à ¢Ã¢â€š ¬Ã‚ ¢ Prerouting Standard Cells: To preroute standard cells, use the preroute_standard_cells command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Low-Power Planning for Multithreshold-CMOS Designs: One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Network Synthesis: As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems. By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing. To perform the PNS, one can run the set of following commands. [16] synthesize_fp_rail set_fp_rail_constraints set_fp_rail_constraints -set_ring set_fp_block_ring_constraints set_fp_power_pad_constraints set_fp_rail_region_constraints set_fp_rail_voltage_area_constraints set_fp_rail_strategy à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Power Plan: Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail command to transform the IR drop map into a power plan. à ¢Ã¢â€š ¬Ã‚ ¢ Handling TLUPlus Models in Power Network Synthesis: Power network synthesis supports TLUPlus models. set_fp_rail_strategy -use_tluplus true à ¢Ã¢â€š ¬Ã‚ ¢ Checking Power Network Synthesis Integrity: Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas. To Check the PNS Integrity one can run the following set of commands. set_fp_rail_strategy -pns_commit_check_file set_fp_rail_strategy -pns_check_chimney_file set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report set_fp_rail_strategy -pns_check_hor_chimney_layers set_fp_rail_strategy -pns_check_chimney_min_dist set_fp_rail_strategy -pns_check_pad_connection file_name set_fp_rail_strategy -pns_report_pad_connection_limit set_fp_rail_strategy -pns_report_min_pin_width set_fp_rail_strategy -pns_check_hard_macro_connection file_name set_fp_rail_strategy -pns_check_hard_macro_connection_limit set_fp_rail_strategy -pns_report_min_pin_width à ¢Ã¢â€š ¬Ã‚ ¢ Analyzing the Power Network: One perform power network analysis to predict IR drop at different floorplan stages on both complete and incomplete power nets in the design. To perform power network analysis, use the analyze_fp_rail command. To add virtual pads, use the create_fp_virtual_pad command. To ignore the hard macro blockages, use the set_fp_power_plan_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Viewing the Analysis Results: When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed. à ¢Ã¢â€š ¬Ã‚ ¢ Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies: To get a report of the current values of the strategies used by power network synthesis and power network analysis by using the report_fp_rail_strategy command. [16] 5.9 Performing Prototype Global Routing One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion hot spots that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing. To perform global routing, use the route_fp_proto command. 5.10 Performing Hierarchical Clock Planning This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Clock Planning Options: To set clock planning options, use the set_fp_clock_plan_options command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Clock Planning Operations: To perform clock planning operations, use the compile_fp_clock_plan command. à ¢Ã¢â€š ¬Ã‚ ¢ Generating Clock Tree Reports: To generate clock tree reports, use the report_clock_tree command. à ¢Ã¢â€š ¬Ã‚ ¢ Using Multivoltage Designs in Clock Planning: Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning: With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16] 5.11 Performing In-Place Optimization In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. T

the fall of rome :: essays research papers

The Fall of Rome   Ã‚  Ã‚  Ã‚  Ã‚  Did the Roman Empire deserve to Fall? No, The achievements of the Roman Empire were unmatched at its time. Many things it accomplished are ideas and ways of life that did not become widespread until after its fall. The Roman Empire would have made the advancement of people in Europe much faster.   Ã‚  Ã‚  Ã‚  Ã‚  The Roman Empire was the most modern ancient empire. It made many advancements in the arts and sciences. It had many great poets, philosophers, artists, and engineers. The Romans encouraged learning and supported any who endeavored to make discoveries or technological improvement. If the Roman Empire had not fallen, the world, from a scientific stand point would be very different today. The Roman Empire would have made discoveries and scientific advancements before the Dark Ages. During the Dark Ages no scientific studies or appreciation of the arts took place. For almost an entire millennium humans made no advancements. The barbarians, who destroyed Rome, destroyed it to take its wealth not its knowledge. The knowledge that was lost was not resurrected until the Renaissance. Technological improvement was at a standstill. If the Roman empire had lasted, Europe would not have fallen into that dark period. Rome would have kept modernizing. Today, we could be at a te chnological level we may not reach for many years. The Romans made advancements in the field of medicine. Today we could have had cures for many diseases had the empire not fallen.   Ã‚  Ã‚  Ã‚  Ã‚  The Roman empire was a democracy. It was one of the first of its kind. It could have stood as a model for all the kingdoms and monarchies across the world. Human rights were existent at Rome hundreds of years before any other place around the world. The Roman people were represented in their government and had power. Many people around the world who were persecuted under dictators and monarchies could have looked at Rome as an example of what a better form of government is. It took the rest of the world more than another millennia to form another democracy. The Roman Government had three parts. These three parts used a system of checks and balances just as a modern democracy does today. The first government to adopt this system since Rome was England, when it adopted its two houses of parliament. After the fall of Rome, anarchy took place in the parts of Europe that it occupied.

Family Systems Essay

Family systems theory was founded by Dr. Murray Bowen. He suggested that the connections and reactions found within a family system creates interdependence on one another. He based his theory on the natural emotional connections with the family. He continued to build upon it as time went on. After Bowen there were several other theorists who used Bowen’s theory as a base, and built off of it. Bowen created his theory based on eight major concepts. They are as follows; Differentiation of Self, Nuclear Family Emotional System, Triangles, Family Projection Process, Multigenerational Transmission Process, Emotional Cutoff, Sibling Position, Societal Emotional Process. The core concept in Bowenian theory is Differentation of Self, this says that the more developed someone’s â€Å"self† is that less impact society and others will have on them. â€Å"The basic building blocks of a â€Å"self† are inborn, but an individual’s family relationships during childhood and adolescence primarily determine how much â€Å"self† he develops† (thebowencenter.com) This concept can be seen as a self-esteem issue. Bowen says that someone with a poor sense of self will quickly conform to others thought and opinions. While someone with a secure sense of â€Å"self† is able to keep that secure thorough social influences. He created a scale that meas ured differentiating self it was measured 0-100. 0-25 were the people with the lowest sense of self, these people liked to be â€Å"comfortable† and did so with self-sacrifice. While people above 60 were rare, they had an extreme sense of self, and were free from societal emotional control and did not control others. The second concept is, Nuclear Family Emotional System which is based on four basic relationship patterns;. marital conflict, dysfunction in one spouse, impairment in one or more children, and emotional distance. Marital conflict is caused by the externalizing of anxiety and emotions caused by family stress. Each spouse presents this in different ways but, the common behaviors include; need for control, knit picking, and resistance to each other. Marital conflict can lead to a breakdown in the family system as well as a marriage. Secondly, dysfunction in one spouse is when one spouse tries  to conform the other to think and act the way they do. The controlling spouse in this situation over bears the other spouse making them act and think in ways they may otherwise not. This can lead to anxiety, tension, and possibly psychiatric or mental dysfunction. Thirdly, impairment in one or more children, can cause excessive attention to the impaired child, causing them to act out and interna lize family tension more then the other children, because they feel like the spotlight is on them. The last relationship pattern is emotional distance. This is a basic pattern seen when the relationships within the family become to intense and people start to distance themselves to lessen the intensity of the relationship. The third concept is Triangles, which are a single relationship with three people involved. Triangles can be great when there is no tension, but can cause a break down in the family system when tension is present. Triangles in tension situations, have insiders and outsiders. The outsiders are trying to get in and the insiders are trying to get out. An example I found of this was a child whose parents were focusing on what was wrong with his so much that he started to rebel. He felt under so much pressure that he was trying to get â€Å"outside† the triangle to relieve some of the pressure. Triangles play an important role in family systems as well as in therapy. The fourth Bowenian concept is, Family projection process which is the process of the parents transmitting there emotional problems to the child. The projection process follows three steps. â€Å"(1) the parent focuses on a child out of fear that something is wrong with the child; (2) the parent interprets the child’s behavior as confirming the fear; and (3) the parent treats the child as if something is really wrong with the child.† (thebowencenter.com) This process can cause the child to feel insecure when attention is not focused on them. There are so many different situation that fall under this projection umbrella. An example could be, a mother feels depressed therefore, she feels the child is depressed and treats the child accordingly. This can also be seen in extreme cases where a mother favors a certain child, and the father sees the child-mother combination as one unit and take his anger towards the mother out on the child. The fifth concept is, Multigeneration al transmission process which says â€Å"how small differences in the levels of differentiation between parents and their offspring lead over many generations to marked differences in differentiation among the  members of a multigenerational family.† (Schara, Blog 2013) Bowen feels that the way people react to situations and relationships is based on a multigenerational transmission of behaviors and emotions. The sixth concept, Emotional cutoff, is simple. Simply speaking people emotionally cutoff other family members instead of resolving the conflicts within the relationship/s. The seventh concept, Sibling position, says that your birth order effects the way you view the world. Oldest siblings tend to be leaders, where youngest siblings tend to be followers. This isn’t always true because can be effected by parental emotions and behaviors. Bowen used psychologist Walter Toman’s research to help him form his theory on sibling position. Examples used; if an oldest sibling is focused on by the parents growing up, then they may not be able to take leadership or make their own decisions. This leaves the â€Å"leadership† role to the younger sibling therefore, putting them in the â€Å"oldest† leadership type role. Where people are in sibling position can effect their marriage, their parenting skills, and of course the family dynamics. The last concept in Bowenian theory is, societal emotional process. This concept tells us how the emotional system controls behavior on a societal level. This is similar to that within a family system, which can be progressive or regressive. Societies go through progressions and regressions constantly. If a society is going through a progression, or regression, it can effect the entire society including all of the major branches and boiling down into the individual family systems. All of these major concepts in Bowenian theory are based on the emotions and behaviors of each individual and their effects on the family system. Bowen was a big believer in the family being seen as one cohesive unit and working towards homeostasis. The basic techniques used in Family systems theory are; detriangulation, nonanxious presence, genograms, coaching, reframing, power differential, and the purser-distancer concept. All of these techniques are used to reach the common goal of homeostasis within the family system. In regards to Detriangualtion, this is when a therapist breaks up a triangular relationship between three people in the family. By having one person within the triangle take a stand on an issue, that is not agreed upon by the other two people in the triangle. Therefore, creating a sense of self within that one person and breaking the give and take relationship in the le. â€Å"In Bowenian family therapy, it is argued that a  conflict between two people will resolve itself in the presence of a third person who can avoid emotional participation with either while relating actively to both.† (Bowen 1978) As a Bowenion therapist you must take on the role of the non-anxious presence. This is when a therapist keeps a sense of calm throughout the session regardless of the circumstances. A non-anxious presence can bring peace to the family involved and help them to open up in session. A n anxious therapist can inflict unneeded chaos and stress for obvious reasons. A building block tool used in the Bowen Family Systems therapy is a genogram. When the family comes in for intake, most therapists will create a genogram. This is a multigenerational map of the family that documents mental illness, substance abuse, medical issues, relationships, and some events tied to specific family members. A genogram can give the therapist a sense of what they need to address within the family system. Family Systems theory uses coaching as a way to help the families through tough times, and provides them with tools to succeed as a family unit. Coaching can help by giving families a way to understand each others interworking’s and hopefully see each other through clearer light. The goal of coaching a family would be to establish a stronger sense of self while strengthening the family system. Reframing takes place when the family needs to change the way they look at each other or the unit as a whole. Reframing a relationship takes hard work but can bring about peace and reduce tension within the family. In order to reframe a relationship or many the therapist must reinterpret a families situation to make them more open to solution. â€Å"Reframing is a type of communication that can help family members better understand the concerns and intentions behind the misconstrued words.† (Jeanty, Jacqueline) An example of reframing, is a child who is constantly badgering their mother about quitting smoking. Once the situation is reframed it is easier to see that the child is scared and cares deeply about the mothers health, which is why they continued to badger. Power Differential,